Methods of forming different finfet devices having different fin heights and an integrated circuit product containing such devices

ABSTRACT

One illustrative method disclosed herein includes forming a plurality of trenches in a plurality of active regions of a substrate that defines at least a first plurality of fins and a second plurality of fins for first and second FinFET devices, respectively, forming liner materials adjacent to the first and second plurality of fins, wherein the liner materials adjacent the first fins and the second fins have a different thickness. The method also includes removing insulating material to expose portions of the liner materials, performing an etching process to remove portions of the liner materials so as to expose at least one fin in the first plurality of fins to a first height and at least one of the second plurality of fins to a second height that is different from the first height.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Generally, the present disclosure relates to the manufacture ofsemiconductor devices, and, more specifically, to various methods offorming 3D semiconductor devices, such as FinFET devices, whereindifferent FinFET devices have different fin heights, and to anintegrated circuit product that contains such FinFET devices.

2. Description of the Related Art

The fabrication of advanced integrated circuits, such as CPU's, storagedevices, ASIC's (application specific integrated circuits) and the like,requires the formation of a large number of circuit elements in a givenchip area according to a specified circuit layout, wherein so-calledmetal oxide field effect transistors (MOSFETs or FETs) represent oneimportant type of circuit element that substantially determinesperformance of the integrated circuits. A FET is a planar device thattypically includes a source region, a drain region, a channel regionthat is positioned between the source region and the drain region, and agate electrode positioned above the channel region. Current flow throughthe FET is controlled by controlling the voltage applied to the gateelectrode. If there is no voltage applied to the gate electrode, thenthere is no current flow through the device (ignoring undesirableleakage currents, which are relatively small). However, when anappropriate voltage is applied to the gate electrode, the channel regionbecomes conductive, and electrical current is permitted to flow betweenthe source region and the drain region through the conductive channelregion.

To improve the operating speed of FETs, and to increase the density ofFETs on an integrated circuit device, device designers have greatlyreduced the physical size of FETs over the years. More specifically, thechannel length of FETs has been significantly decreased, which hasresulted in improving the switching speed of FETs. However, decreasingthe channel length of a FET also decreases the distance between thesource region and the drain region. In some cases, this decrease in theseparation between the source and the drain makes it difficult toefficiently inhibit the electrical potential of the source region andthe channel from being adversely affected by the electrical potential ofthe drain. This is sometimes referred to as a so-called short channeleffect, wherein the characteristic of the FET as an active switch isdegraded.

In contrast to a FET, which has a planar structure, a so-called FinFETdevice has a three-dimensional (3D) structure. More specifically, in aFinFET, a generally vertically positioned fin-shaped active area isformed and a gate electrode encloses both sides and an upper surface ofthe fin-shaped active area to form a tri-gate structure so as to use achannel having a three-dimensional structure instead of a planarstructure. In some cases, an insulating cap layer, e.g., siliconnitride, is positioned at the top of the fin and the FinFET device onlyhas a dual-gate structure. Unlike a planar FET, in a FinFET device, achannel is formed perpendicular to a surface of the semiconductingsubstrate so as to reduce the physical size of the semiconductor device.Also, in a FinFET, the junction capacitance at the drain region of thedevice is greatly reduced, which tends to reduce at least some shortchannel effects. When an appropriate voltage is applied to the gateelectrode of a FinFET device, the surfaces (and the inner portion nearthe surface) of the fins, i.e., the substantially vertically orientedsidewalls and the top upper surface of the fin with inversion carriers,contributes to current conduction. In a FinFET device, the“channel-width” is approximately two times (2×) the vertical fin-heightplus the width of the top surface of the fin, i.e., the fin width.Multiple fins can be formed in the same foot-print as that of a planartransistor device. Accordingly, for a given plot space (or foot-print),FinFETs tend to be able to generate significantly stronger drivecurrents than planar transistor devices. Additionally, the leakagecurrent of FinFET devices after the device is turned “OFF” issignificantly reduced as compared to the leakage current of planar FETsdue to the superior gate electrostatic control of the “fin” channel onFinFET devices. In short, the 3D structure of a FinFET device is asuperior MOSFET structure as compared to that of a planar FET,especially in the 20 nm CMOS technology node and beyond.

One process flow that is typically performed to form FinFET devicesinvolves forming a plurality of trenches in the substrate to define theareas where STI regions will be formed and to define the initialstructure of the fins. These trenches are typically formed in thesubstrate during the same process operation for processing simplicity.The trenches have a target depth that is sufficient for the needed finheight and deep enough to allow formation of an effective STI region.After the trenches are formed, a layer of insulating material, such assilicon dioxide, is formed so as to overfill the trenches. Thereafter, achemical mechanical polishing (CMP) process is then performed toplanarize the upper surface of the insulating material with the top ofthe fins (or the top of a patterned hard mask). Thereafter, an etch-backprocess is performed to recess the layer of insulating material betweenthe fins and thereby expose the upper portions of the fins, whichcorresponds to the final fin height of the fins.

Given the way that fins are typically formed, a conventional FinFETdevice has a fixed fin height, i.e., all of the fins have the sameheight. Thus, the total channel width of a multiple fin FinFET device isequal to the number of fins (“X”) times the channel width provided byeach fin, i.e., each fin provides a channel length equal to two times(2×) the vertical fin-height plus the width of the top surface of thefin. That is, the total channel width of a multiple fin device is fixedby the fin height and number of fins. Importantly, using traditionalmanufacturing techniques, a FinFET device with multiple fins, e.g., atwo-fin device, cannot be manufactured such that the total channel widthof the device is equal to, for example, 1.5 times the total height ofthe two fins in the two-fin device. This lack of flexibility inmanufacturing FinFET devices provides designers with less flexibilitythan would otherwise be desired in designing complex integratedcircuits.

In designing digital circuits, one parameter that is very important isthe desired drive current produced by individual transistors (FETsand/or FinFETs) and the overall drive current needed or produced by agiven circuit arrangement. In circuits involving planar FETs, devicedesigners can produce FETs that generate a virtually desired fractionallevel of drive current. That is, for planar FETs, the drive current ofthe FET may be readily adjusted to virtually any value by simplychanging the gate width of the planar FET. For example, if a designerdesires a FET with ½ strength drive current, then the gate width of aplanar FET with an integer drive strength of 1 is simply reduced byhalf. Similarly, if twice the drive strength of a planar FET isrequired, then the gate width of the FET is doubled. Of course,increasing the gate width of a planar FET device consumes more plotspace, but the ability to produce planar FETs with desired fractionaldrive currents gives device designers great flexibility in designingintegrated circuits. Many digital and analog circuits are based upondesigns that involve fractional drive current strengths. However, asdiscussed above, with FinFETs, the channel width is fixed by the heightof the fin.

Additionally, for some integrated circuit products, it is necessary thatone FinFET based device produce more drive current than another FinFETdevice in the same circuit. For example, in an SRAM product, there is anoptimized drive current ratio between the so-called pass-gatetransistor, pull-up transistor and pull-down transistor. In practicalterms, given the fixed fin height of FinFET devices, the pass-gatetransistor must be physically different in plot-space size than thepull-up transistor to get the desired difference in drive current, e.g.,the transistors consume different amounts of plot space on thesubstrate. Unfortunately, this size differential can adversely affectpatterning operations as etching processes may be affected by locallyvarying densities in circuit features. Such variations in the resultingdevice structures can adversely affect device performance.

Device manufacturers are under constant pressure to produce integratedcircuit products with increased performance and lower production costsrelative to previous device generations. Thus, device designers spend agreat amount of time in an effort to maximize device performance whileseeking ways to reduce manufacturing costs and improve manufacturingreliability. As it relates to 3D devices, device designers have spentmany years and employed a variety of techniques in an effort to improvethe performance capability and reliability of such devices.

The present disclosure is directed to various methods of forming 3Dsemiconductor devices, such as FinFET devices, wherein different FinFETdevices have different fin heights, and to an integrated circuit productthat contains such FinFET devices that may solve or reduce one or moreof the problems identified above.

SUMMARY OF THE INVENTION

The following presents a simplified summary of the invention in order toprovide a basic understanding of some aspects of the invention. Thissummary is not an exhaustive overview of the invention. It is notintended to identify key or critical elements of the invention or todelineate the scope of the invention. Its sole purpose is to presentsome concepts in a simplified form as a prelude to the more detaileddescription that is discussed later.

Generally, the present disclosure is directed to various methods offorming 3D semiconductor devices, such as FinFET devices, whereindifferent FinFET devices have different fin heights, and to anintegrated circuit product that contains such FinFET devices. Oneillustrative method disclosed herein for forming an integrated circuitproduct includes performing at least one first etching process through apatterned mask layer to form a plurality of trenches in a plurality ofactive regions of the substrate that defines at least a first pluralityof fins and a second plurality of fins for first and second FinFETdevices, respectively, forming liner material adjacent to the firstplurality of fins to a first thickness, forming liner material adjacentto the second plurality of fins to a second thickness that is differentfrom the first thickness, and forming insulating material in thetrenches adjacent the liner materials and above the mask layer. Themethod also includes performing at least one process operation to removeportions of the layer of insulating material and to expose portions ofthe liner materials, performing at least one second etching process toremove portions of the liner materials and the mask layer so as toexpose at least one fin in the first plurality of fins to a first heightand at least one of the second plurality of fins to a second height thatis different from the first height, performing at least one thirdetching process on the insulating material to thereby define areduced-thickness layer of insulating material and forming gatestructures around the first plurality of fins and the second pluralityof fins.

One illustrative integrated circuit product disclosed herein includes afirst FinFET device formed above a first active region of asemiconductor substrate, wherein the first FinFET device includes afirst plurality of fins, and wherein at least one of the first pluralityof fins has a first fin height, a first trench positioned between thefirst plurality of fins, wherein the first trench has a first generallyU-shaped liner material positioned in a bottom of the first trench, anda second FinFET device formed above a second active region of thesemiconductor substrate, wherein the second FinFET device includes asecond plurality of fins, wherein at least one of the second pluralityof fins has a second fin height that is different from the first finheight and a second trench positioned between the second plurality offins, wherein the second trench has a second generally U-shaped linermaterial positioned in a bottom of the second trench.

Another illustrative integrated circuit device disclosed herein includesa first FinFET device positioned above a first active region of asemiconductor substrate, wherein the first FinFET device includes atleast one first fin having a first fin height, and a second FinFETdevice positioned above a second active region of the semiconductorsubstrate, wherein the second FinFET device includes at least one secondfin having a second fin height, wherein the first and second fin heightsare different.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be understood by reference to the followingdescription taken in conjunction with the accompanying drawings, inwhich like reference numerals identify like elements, and in which:

FIGS. 1A-1I depict various illustrative methods disclosed herein forforming different FinFET devices such that they have different finheights and to an integrated circuit product that contains such FinFETdevices.

While the subject matter disclosed herein is susceptible to variousmodifications and alternative forms, specific embodiments thereof havebeen shown by way of example in the drawings and are herein described indetail. It should be understood, however, that the description herein ofspecific embodiments is not intended to limit the invention to theparticular forms disclosed, but on the contrary, the intention is tocover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION

Various illustrative embodiments of the invention are described below.In the interest of clarity, not all features of an actual implementationare described in this specification. It will of course be appreciatedthat in the development of any such actual embodiment, numerousimplementation-specific decisions must be made to achieve thedevelopers' specific goals, such as compliance with system-related andbusiness-related constraints, which will vary from one implementation toanother. Moreover, it will be appreciated that such a development effortmight be complex and time-consuming, but would nevertheless be a routineundertaking for those of ordinary skill in the art having the benefit ofthis disclosure.

The present subject matter will now be described with reference to theattached figures. Various structures, systems and devices areschematically depicted in the drawings for purposes of explanation onlyand so as to not obscure the present disclosure with details that arewell known to those skilled in the art. Nevertheless, the attacheddrawings are included to describe and explain illustrative examples ofthe present disclosure. The words and phrases used herein should beunderstood and interpreted to have a meaning consistent with theunderstanding of those words and phrases by those skilled in therelevant art. No special definition of a term or phrase, i.e., adefinition that is different from the ordinary and customary meaning asunderstood by those skilled in the art, is intended to be implied byconsistent usage of the term or phrase herein. To the extent that a termor phrase is intended to have a special meaning, i.e., a meaning otherthan that understood by skilled artisans, such a special definition willbe expressly set forth in the specification in a definitional mannerthat directly and unequivocally provides the special definition for theterm or phrase.

In general, the present disclosure is directed to various methods offorming 3D semiconductor devices, such as FinFET devices, whereindifferent FinFET devices have different fin heights, and to anintegrated circuit product that contains such FinFET devices. Moreover,as will be readily apparent to those skilled in the art upon a completereading of the present application, the present method is applicable toa variety of devices, including, but not limited to, logic devices,memory devices, etc., and the methods disclosed herein may be employedto form N-type or P-type semiconductor devices. With reference to theattached figures, various illustrative embodiments of the methods anddevices disclosed herein will now be described in more detail.

The attached drawings depict one illustrative embodiment of a novelintegrated circuit product 100 that is generally comprised of a firstFinFET device 100A and a second FinFET device 100B that are formed aboveseparate active regions 14A, 14B, respectively, of a semiconductorsubstrate 14. As will be recognized by those skilled in the art after acomplete reading of the present application, the FinFET devices 100A,100B may be either the same type device, e.g., both N-type devices, orthey may be opposite type devices, i.e., one a P-type device and one anN-type device. In one particular example, one of the devices 100A, 100Bmay be a so-called pull-down transistor of an SRAM circuit, while theother device may be a so-called pass-gate transistor of such an SRAMcircuit. As described more fully below, the methods disclosed hereinprovide device designers with more flexibility as it relates tomanufacturing integrated circuit products. As one example, the methodsdisclosed herein that enable formation of different FinFET devices withdifferent fin heights may allow devices designers to make the FinFETdevices 100A, 100B the same physical size (so that they consume the sameamount of plot space on the substrate), yet still produce differentdrive currents by virtue of adjusting the fin heights on the two devicesto different heights. Such uniformity in the size of the FinFET devices100A, 100B may make integrated circuit fabrication easier and may resultin fewer errors due to the substantial uniformity in the size of theFinFET devices 100A, 100B. Additional advantages of the methods andproducts disclosed herein will be appreciated by those skilled in theart after a complete reading of the present application.

FIG. 1A schematically depicts one illustrative embodiment of a novelintegrated circuit product 100 disclosed herein at a point offabrication wherein a plurality of trenches 12 have been formed in bothof the active regions 14A, 14B of a bulk semiconducting substrate 14 byperforming at least one etching process through a patterned hard masklayer 16, e.g., a patterned layer of silicon nitride. This results inthe formation of a plurality of illustrative fins 20 in the substrate14. A first group of fins 20A-C is formed above the first active region14A where the FinFET device 100A will be formed, while a second group offins 20D-F are formed above the second active region 14B where theFinFET device 100B will be formed. As noted above, each of the FinFETdevices 100A, 100B may be either an N-type device or a P-type FinFETdevice, and they may be formed using either so-called “gate-first” or“replacement gate” (“gate-last”) techniques. In the examples depictedherein, the illustrative FinFET devices 100A, 100B will be comprised ofthree illustrative fins 20, i.e., fins 20A-C for the first FinFET device100A and fins 20D-F for the second FinFET device 100B. However, as willbe recognized by those skilled in the art after a complete reading ofthe present application, the presently disclosed inventions may beemployed in manufacturing FinFET devices having any desired number offins. Moreover, the FinFET devices 100A, 100B need not each have thesame number of fins 20, although such a situation may occur in someapplications. The depicted active regions 14A, 14B may be adjacent oneanother on the substrate 14 or they may be spaced apart from one anotherby any desired distance. Isolation regions (not shown) may be formed forthe FinFET devices 100A, 100B after the formation of the trenches 12using techniques that are well known to those skilled in the art. So asnot to obscure the present invention, such isolation regions that areformed to electrically isolate the FinFET devices 100A, 100B from oneanother are not depicted in the attached drawings.

The substrate 14 may have a variety of configurations, such as thedepicted bulk substrate configuration. The substrate 14 may be made ofsilicon or it may be made of materials other than silicon. Thus, theterms “substrate” or “semiconducting substrate” should be understood tocover all semiconducting materials and all forms of such materials.Additionally, the overall size, shape and configuration of the trenches12 and fins 20 may vary depending on the particular application. Thedepth and width of the trenches 12 may also vary depending upon theparticular application. In one illustrative embodiment, based oncurrent-day technology, the depth of the trenches 12 may range fromapproximately 30-200 nm and the width of the trenches 12 may range fromabout 20-50 nm. In some embodiments, the fins 20 may have a width withinthe range of about 5-30 nm. In the illustrative examples depicted inmost of the attached drawings, the trenches 12 and fins 20 are all of auniform size and shape. However, as discussed more fully below, suchuniformity in the size and shape of the trenches 12 and the fins 20 isnot required to practice at least some aspects of the inventionsdisclosed herein. In the attached figures, the trenches 12 are depictedas having been formed by performing an anisotropic etching process thatresults in the trenches 12 having a schematically depicted, generallyrectangular configuration. In an actual real-world device, the sidewallsof the trenches 12 may be somewhat inwardly tapered, although thatconfiguration is not depicted in the attached drawings. In some cases,the trenches 12 may have a reentrant profile near the bottom of thetrenches 12. To the extent the trenches 12 are formed by performing awet etching process, the trenches 12 may tend to have a more roundedconfiguration or non-linear configuration as compared to the generallyrectangular configuration of the trenches 12 that are formed byperforming an anisotropic etching process. Thus, the size andconfiguration of the trenches 12, and the manner in which they are made,as well as the general configuration of the fins 20, should not beconsidered a limitation of the present invention. For ease ofdisclosure, only the substantially rectangular trenches 12 will bedepicted in the subsequent drawings.

The patterned hard mask layer 16 is intended to be representative innature as it may be comprised of a variety of materials, such as, forexample, silicon nitride, silicon oxynitride, Al₂O₃, HfO₂, etc.Moreover, the patterned hard mask layer 16 may be comprised of multiplelayers of material. The patterned hard mask layer 16 may be formed bydepositing the layer(s) of material that comprise the patterned hardmask layer 16 and thereafter directly patterning the patterned hard masklayer 16 using known photolithography and etching techniques.Alternatively, the patterned hard mask layer 16 may be formed by usingknown sidewall image transfer techniques. Thus, the particular form andcomposition of the patterned hard mask layer 16 and the manner in whichit is made should not be considered a limitation of the presentinvention. In the case where the patterned hard mask layer 16 iscomprised of one or more hard mask layers, such layers may be formed byperforming a variety of known processing techniques, such as a chemicalvapor deposition (CVD) process, an atomic layer deposition (ALD)process, an epitaxial deposition process (EPI), or plasma enhancedversions of such processes, and the thickness of such a layer(s) mayvary depending upon the particular application.

FIG. 1B depicts the integrated circuit product 100 after a conformaldeposition process, e.g., a chemical vapor deposition (CVD) process, anatomic layer deposition (ALD) process, etc., has been performed to forma first liner layer 22 on the fins 20 and in the trenches 12 for boththe first FinFET device 100A and the second FinFET device 100B. Morespecifically, in the depicted example, the first liner layer 22 isformed above the patterned hard mask layer 16, on the sidewalls of allof the fins 20 (20A-F) and in the trenches 12 in both active regions14A-B. The thickness 22T of the first liner layer 22 may vary dependingupon the particular application, e.g., it may have a thickness of about2-5 nm. As described more fully below, using the processes describedherein and in the illustrative embodiment depicted herein, the finheight of the fins 20A-C of the first FinFET device 100A are set, basedin part, by selecting the desired thickness 22T of the first liner layer22. In general, the first liner layer 22 may be made of a material thatmay be selectively etched relative to the insulating material that willbe used to fill the portions of the trenches 12 in a later processoperation. For example, the first liner layer 22 may be comprised ofsilicon nitride, silicon carbon nitride, silicon boron nitride, a dopednitride, silicon oxynitride, Al₂O₃, HfO₂, boron or phosphorous dopedsilicon dioxide, etc. The basic principle involved is that the linerlayer 22 needs to be selectively etchable relative to the hard mask 16and the insulating material that will ultimately be formed to fill theremaining portions of the trenches 12 in a subsequent process operationto be more fully described below. In one particularly illustrativeembodiment, the patterned hard mask layer 16 may be made of siliconnitride and the first liner layer 22 may be made of aluminum oxide.

FIG. 1C depicts the integrated circuit product 100 after several processoperations have been performed. First, a patterned masking layer (notshown), e.g., a patterned photoresist mask, was formed above the firstFinFET device 100A and exposed the second FinFET device 100B for furtherprocessing, i.e., the portions of the first liner layer 22 above thefins 20D-F was exposed for further processing. Thereafter, an etchingprocess was performed through the patterned mask layer to remove thefirst liner layer 22 formed above the second active region 14B.Thereafter, the masking layer was removed. Such processing operationsresult in the structure depicted in FIG. 1C. Importantly, this etchingprocess clears the liner material from the sidewalls of the fins 20D-Fof the second FinFET device 100B while leaving the liner material on thefins 20A-C of the first FinFET device 100A. Of course, if desired, themasking layer could have equally been formed above the second FinFETdevice 100B and the liner material could have been removed from the fins20A-C of the first FinFET device 100A. Thus, the present inventionshould not be considered to be limited to performing the processoperations in the order depicted herein, or on the particular devicesshown in the illustrative processing sequence depicted herein.

FIG. 1D depicts the integrated circuit product 100 after anotherconformal deposition process, e.g., a chemical vapor deposition (CVD)process, an atomic layer deposition (ALD) process, etc., has beenperformed to form a second liner layer 24 above the remaining portion ofthe first liner layer 22 on the fins 20A-C of the first FinFET device100A and in the trenches 12 adjacent the exposed fins 20D-F of thesecond FinFET device 100B. The thickness 24T of the second liner layer24 may vary depending upon the particular application, e.g., it may havea thickness of about 2-5 nm. In some cases, the thickness 24T of thesecond liner layer 24 may be about the same as the thickness 22T (FIG.1B) of the first liner layer 22, although such a situation is notrequired to practice the inventions disclosed herein. As described morefully below, using the processes described herein, the fin height of atleast some of the fins 20A-C of the first FinFET device 100A are set,based, in part, upon the combined thicknesses 22T, 24T of the first andsecond liner layers 22, 24, respectively, while the fin height of atleast some of the fins 20D-F are set, based, in part, upon the thickness24T of only the second liner layer 24. In general, the second linerlayer 24 may be made of a material that may be selectively etchedrelative to the insulating material that will be used to fill theportions of the trenches 12 in a later process operation. For example,the second liner layer 24 may be comprised of silicon nitride, siliconcarbon nitride, silicon boron nitride, a doped nitride, siliconoxynitride, Al₂O₃, HfO₂, boron or phosphorous doped silicon dioxide,etc. In some cases, the first liner layer 22 and the second liner layer24 may be made of the same material, although such a situation is notrequired to practice the inventions disclosed herein. In oneparticularly illustrative embodiment, the patterned hard mask layer 16may be made of silicon nitride, while the first liner layer 22 and thesecond liner layer 24 may both be made of aluminum oxide.

FIG. 1E depicts the integrated circuit product 100 after several processoperations have been performed. First, a layer of insulating material 26was deposited so as to overfill the trenches 12 in both the first andsecond active regions 14A, 14B and, thereafter, a CMP process wasperformed on the layer of insulating material 26 in an effort toplanarize the upper surface of the layer of insulating material 26. Inthe case where the active regions 14A, 14B are spaced apart from oneanother, the CMP process results in the substantially planar uppersurfaces depicted in FIG. 1E. In the case where the first and secondactive regions 14A, 14B are formed adjacent to one another (a situationnot shown in the attached drawings), due to the presence of the firstliner layer 22 and the second liner layer 24 above the fins 20A-C, andthe absence of the first liner layer 22 above the fins 20D-F, there maybe some dishing (not shown) of the layer of insulating material 26 inthe transition region between the active regions 14A, 14B. In thedepicted example, the CMP process stops on the second liner layer 24.The layer of insulating material 26 may be comprised of a variety ofdifferent materials, such as silicon dioxide, doped silicon dioxide(doped with carbon, boron or phosphorous), etc., and it may be formed byperforming a variety of techniques, e.g., chemical vapor deposition(CVD), etc. Instead of a CMP process, an etch-back process could beperformed on the layer of insulating material 26 to arrive atsubstantially the same structure as depicted in FIG. 1E.

FIGS. 1F-1G depict an etching process sequence that is performed on theintegrated circuit product 100. Initially, if desired, an optional oxidedeglaze etching process may be performed to insure that all of theinsulating material 26, e.g., silicon dioxide, is removed from the uppersurfaces of the second liner layer 24. In general, the etching processsequence is performed to remove the patterned hard mask 16 and portionsof the first and second liner layers 22, 24 selectively relative to theinsulating material 26. Initially, as shown in FIG. 1F, during a firstportion of the etching sequence, portions of the first and second linerlayers 22, 24 are removed to expose the patterned hard mask layer 16.Depending upon the material of constructions of the patterned hard mask16 and the first and second liner layers 22, 24, some of the patternedhard mask layer 16 may be consumed at the point of fabrication depictedin FIG. 1F, although such consumption in not depicted in the drawings.At this point in the etching sequence, portions of the liner materials,i.e., the liners 22 and/or 24, positioned in the trenches 12 areexposed. Due to the presence of the first liner layer 22 above the fins20A-C of the first FinFET device 100A, after this initial portion of theetching sequence, the surface 24S1 of the second liner layer 24 in thearea around the fins 20D-F of the second FinFET device 100B is at alevel that is below the surface 24S2 of the second liner layer 24 in thearea around the fins 20A-C of the first FinFET device 100A.

FIG. 1G depicts the integrated circuit product 100 at the end of theetching process sequence wherein the first and second liner layers 22,24 have been recessed sufficiently to establish the final exposed firstfin height 20H1 for the fins 20A-C of the first FinFET device 100A and asecond exposed fin height 20H2 for the fins 20D-F of the second FinFETdevice 100B, wherein the first fin height 20H1 is greater than thesecond fin height 20H2. In the depicted example, the etching processsequence results in cavities 30 adjacent the fins 20A-C of the firstFinFET device 100A and cavities 32 adjacent the fins 20D-F of the secondFinFET device 100B. The liner material(s) in the trenches 12 adjacentthe fins 20A-C of the first FinFET device 100A has a thickness 31 thatis greater than the thickness 33 of the liner material(s) in thetrenches 12 adjacent the fins 20D-F of the second FinFET device 100B. Ingeneral, in forming the cavities 30, 32, the etch rate of the linermaterials (liner 22 and/or 24 as the case may be) in the above-describedliner material recessing etch process increases as the width of thecavities 30, 32 increases, which provides a means to effectively controlthe depth of the liner recess. That is, due to the greater width 31 ofthe liner material(s) in the cavities 30 as compared to the width 33 ofthe liner material(s) in the cavities 32, the depth of the cavities 30will be greater than the depth of the cavities 32, which provides aneffective means to control the final fin heights 20H1, 20H2 of the fins20 in the FinFET devices 100A, 100B, respectively. The difference in theeffective etch rate of the etch process in the cavities 30, 32 occupiedby the liner materials of different thicknesses may be referred to as aso-called capillary effect. It should also be noted that the control ofthe fin heights 20H1, 20H2 is not dependent upon the fin pitch of FinFETdevices 100A, 100B that may be located in different regions of theintegrated circuit product 100, since the fin heights 20H1, 20H2 arebased upon applying the above-described capillary effects to remove theliner material(s), irrespective of fin pitch. Stated another way, thegreater the thickness of the liner material in the trenches adjacent aparticular fin, the greater will be the final fin height of the finusing the methods disclosed herein. The increased width due toadditional liner material means that the cavity 30 during the recessetch process is wider, which does not slow the etch rate of the recessetch process as much as a narrower cavity 32 that results from the useof a thinner liner material(s), e.g., only the second liner layer 24. Byselecting the appropriate target thickness 22T (FIG. 1B) and/or 24T(FIG. 1D) (either a specific number or a range) of the first and secondliner layers 22, 24, the target final fin heights 20H1, 20H2 for theFinFET devices 100A, 100B, respectively, may be set and controlled usingthe methods disclosed herein. For example, using the methods disclosedherein, setting the target thickness 31 of the liner material(s)adjacent the fins 20A-C of the first FinFET device 100A at values A, Band C results in the fins 20A-C of the FinFET device 100 having asubstantially uniform final fin height 20H1 of X₁, X₂ and X₃,respectively. Similarly, using the methods disclosed herein, setting thetarget thickness 33 of the liner material(s) adjacent the fins 20D-F ofthe second FinFET device 100B at values D, E and F results in the fins20D-F of the second FinFET device 100B having a substantially uniformfinal fin height 20H2 of Y₁, Y₂ and Y₃, respectively. The relationshipbetween the thicknesses of the liner materials 31, 33 and the associatedfinal fin heights 20H1, 20H2 may vary depending upon a variety offactors, e.g., the materials used for the liner material(s), theetchants used in the recess etch process, the geometry of the trench 12,etc. Moreover, the relationship between the thicknesses of the linermaterials 31, 33 and the final fin heights 20H1, 20H2 may not be linear.Accordingly, it is anticipated that, in implementing the presentinventions, testing may be required to establish the exact parametersof, for example, liner material(s), liner thicknesses and etchingprocess conditions and materials to arrive at a solution tailored forthe first FinFET device 100A and the second FinFET device 100B of theintegrated circuit product 100.

FIG. 1H depicts the integrated circuit product 100 at a point infabrication wherein a timed etching process has been performed on thelayer of insulating material 26 to reduce its thickness and therebydefine a reduced-thickness layer of insulating material 26R. Thisprocess results in the formation of local isolation regions 37A, 37B(for the FinFET devices 100A, 100B, respectively) in the bottom of thetrenches 12 that have slightly different configurations. The localisolation region 37A is generally comprised of a first generally “U”shaped dual liner configuration with a pair of spaced-apartsubstantially upstanding or vertical leg portions (the combinedvertically oriented portions of the liners 22, 24) that are connected bya substantially horizontal portion (the combined horizontally orientedportions of the liners 22, 24). This first generally U-shaped linerdefines a first liner cavity 39. A portion of the layer of insulatingmaterial 26R is positioned in the first liner cavity 39 defined. Thelocal isolation region 37B is generally comprised of a second generally“U” shaped single liner configuration with a pair of spaced-apartsubstantially upstanding or vertical leg portions of just the secondliner layer 24 that are connected by a substantially horizontal portionof the second liner layer 24. This second generally U-shaped linerdefines a second liner cavity 41. A portion of the layer of insulatingmaterial 26R is positioned in the second liner cavity 41 defined.

The process of recessing the layer of insulating material 26 may beaccurately controlled such that its post-recessing surface 26S may bepositioned at any desired location. In the depicted example, therecessing etch process is performed for a sufficient duration such thatthe post-recessing surface 26S is positioned substantially even with theupper surfaces of the liner materials of the local isolation regions37A. In practice, the post-etch surface 26S may be located at the leveldepicted in FIG. 1H or at a level corresponding to the dashed line 26Xin FIG. 1H.

FIG. 1I depicts the integrated circuit product 100 at a later stage ofmanufacturing wherein illustrative final gate structures 40 comprised ofan illustrative gate insulation layer 40A and an illustrative gateelectrode 40B have been formed on the FinFET devices 100A, 100B. Thefinal gate structure 40 may be formed using so-called “gate-first” or“replacement-gate” (“gate-last”) techniques. An illustrative gate caplayer (not shown) may also be formed above the illustrative gateelectrode 40B. The gate insulation layer 40A may be comprised of avariety of different materials, such as, for example, silicon dioxide, aso-called high-k (k greater than 10) insulation material (where k is therelative dielectric constant), etc. The thickness of the gate insulationlayer 40A may also vary depending upon the particular application, e.g.,it may have a thickness of about 1-2 nm. Similarly, the gate electrode40B may also be of a variety of conductive materials, such aspolysilicon or amorphous silicon, or it may be comprised of one or moremetal layers that act as the gate electrode 40B. As will be recognizedby those skilled in the art after a complete reading of the presentapplication, the gate structure 40 of the FinFET devices 100A, 100Bdepicted in the drawings, i.e., the gate insulation layer 40A and thegate electrode 40B, is intended to be representative in nature. That is,the gate structure 40 may be comprised of a variety of differentmaterials and it may have a variety of configurations. In oneillustrative embodiment, a deposition process may be performed to form agate insulation layer 40A comprised of silicon dioxide. Thereafter, thegate electrode material 40B and the gate cap layer material (not shown)may be deposited above the device 100 and the layers may be patternedusing known photolithographic and etching techniques. In anotherillustrative embodiment, a conformal CVD or ALD process may be performedto form the depicted gate insulation layer 40A comprised of hafniumoxide. Thereafter, one or more metal layers (that will become the gateelectrode 40B) and a gate cap layer material (not shown), e.g., siliconnitride, may be deposited above the FinFET devices 100A, 100B. Ofcourse, the materials of construction for the FinFET devices 100A, 100Bmay be different. At this point, traditional manufacturing techniquesmay be performed to complete the manufacture of the integrated circuitproduct 100. For example, sidewall spacers (not shown) comprised of, forexample, silicon nitride, may be formed adjacent the final gatestructures 40. After the spacers are formed, if desired, an epitaxialgrowth process may be performed to form additional semiconductingmaterial (not shown) on the portions of the fins 20 positioned outsideof the spacers. Additional contacts and metallization layers may then beformed above the FinFET devices 100A, 100B using traditional techniques.

One illustrative method disclosed herein for forming an integratedcircuit product 100 includes performing at least one first etchingprocess through a patterned mask layer 16 to form a plurality oftrenches 12 in the active regions 14A, 14B of the substrate 14 thatdefines at least a first plurality of fins, e.g., fins 20A-C, and asecond plurality of fins, e.g., fins 20D-F, forming liner material(e.g., portions of the liners 22 and 24) adjacent to the first pluralityof fins to a first thickness 31, forming liner material (e.g., portionsof the liner 24) adjacent to the second plurality of fins to a secondthickness 33 that is different from the first thickness, and forminginsulating material 26 in the trenches adjacent the liner materials andabove the mask layer 16. The method also includes performing at leastone process operation to remove portions of the layer of insulatingmaterial 26 and to expose portions of the liner materials, performing atleast one second etching process to remove portions of the linermaterials and the mask layer 16 so as to expose at least one fin in thefirst plurality of fins to a first height 20H1 and at least one of thesecond plurality of fins to a second height 20H2 that is different fromthe first height, performing at least one third etching process on theinsulating material to thereby define a reduced-thickness layer ofinsulating material 26R, and forming gate structures 40 around the firstplurality of fins and the second plurality of fins.

Of course, the methods disclosed herein may also be employed in formingsingle or multiple fin devices. That is, in one embodiment, both of thedevices 100A, 100B may be single fin FinFET devices, or only one of thedevices 100A, 100B may be a single fin device while the other device maybe a multiple fin device. Additionally, as noted above, the methodsdisclosed herein may also be employed to form the devices 100A, 100Bwhere they are each comprised of multiple fins. In general, oneillustrative method disclosed herein includes forming a patterned hardmask layer above a semiconductor substrate, performing at least onefirst etching process through the patterned hard mask layer to form aplurality of trenches in the substrate that define a first fin above afirst active region of the substrate and a second fin formed above asecond active region of the substrate, forming liner material adjacentto at least the first fin to a first thickness, forming liner materialadjacent to at least the second fin to a second thickness that isdifferent from the first thickness, forming a layer of insulatingmaterial in the trenches adjacent the liner materials and above thepatterned hard mask layer, performing at least one process operation toremove portions of the layer of insulating material and to exposeportions of the liner materials, performing at least one second etchingprocess to remove portions of the liner materials and the patterned hardmask layer, wherein removal of the liner materials results in exposingthe first fin to a first height and the second fin to a second heightthat is different from the first height, and performing at least onethird etching process on the layer of insulating material to therebydefine a reduced-thickness layer of insulating material.

One illustrative integrated circuit product 100 disclosed hereinincludes a first FinFET device 100A formed above a first active region14A of a semiconductor substrate 14, wherein the first FinFET device100A includes a first plurality of fins, e.g., fins 20A-C, wherein atleast one of the first plurality of fins has a first fin height 20H1, afirst trench positioned between the first plurality of fins, wherein thefirst trench has a first generally U-shaped liner material positioned ina bottom of the first trench, and a second FinFET device 100B formedabove a second active region 14B of the semiconductor substrate, whereinthe second FinFET device 100B includes a second plurality of fins, e.g.,fins 20D-F, at least one of the second plurality of fins having a secondfin height 20H2, wherein the first and second fin heights are different,and a second trench positioned between the second plurality of fins andwherein the second trench has a second generally U-shaped liner materialpositioned in a bottom of the second trench.

Another illustrative integrated circuit device disclosed herein includesa first FinFET device positioned above a first active region of asemiconductor substrate, wherein the first FinFET device includes atleast one first fin having a first fin height, and a second FinFETdevice positioned above a second active region of the semiconductorsubstrate, wherein the second FinFET device includes at least one secondfin having a second fin height, wherein the first and second fin heightsare different.

The particular embodiments disclosed above are illustrative only, as theinvention may be modified and practiced in different but equivalentmanners apparent to those skilled in the art having the benefit of theteachings herein. For example, the process steps set forth above may beperformed in a different order. Furthermore, no limitations are intendedto the details of construction or design herein shown, other than asdescribed in the claims below. It is therefore evident that theparticular embodiments disclosed above may be altered or modified andall such variations are considered within the scope and spirit of theinvention. Note that the use of terms, such as “first,” “second,”“third” or “fourth” to describe various processes or structures in thisspecification and in the attached claims is only used as a shorthandreference to such steps/structures and does not necessarily imply thatsuch steps/structures are performed/formed in that ordered sequence. Ofcourse, depending upon the exact claim language, an ordered sequence ofsuch processes may or may not be required. Accordingly, the protectionsought herein is as set forth in the claims below.

What is claimed:
 1. A method of forming an integrated circuit product,comprising: forming a patterned hard mask layer above a semiconductorsubstrate; performing at least one first etching process through saidpatterned hard mask layer to form a plurality of trenches in saidsemiconductor substrate that define a first plurality of fins above afirst active region of said substrate and a second plurality of finsabove a second active region of said substrate; forming liner materialadjacent to at least said first plurality of fins to a first thickness;forming liner material adjacent to at least said second plurality offins to a second thickness that is different from said first thickness;forming a layer of insulating material in said trenches adjacent saidliner materials and above said patterned hard mask layer; performing atleast one process operation to remove portions of said layer ofinsulating material and to expose portions of said liner materials;performing at least one second etching process to remove portions ofsaid liner materials and said patterned hard mask layer, wherein removalof said liner materials results in exposing at least one of said firstplurality of fins to a first height and at least one of said secondplurality of fins to a second height that is different from said firstheight; and performing at least one third etching process on said layerof insulating material to thereby define a reduced-thickness layer ofinsulating material.
 2. The method of claim 1, wherein said firstplurality of fins are for a first FinFET device of a first type and saidsecond plurality of fins are for a second FinFET device of a second typethat is opposite to said first type.
 3. The method of claim 1, whereinsaid first plurality of fins are for a first FinFET device and saidsecond plurality of fins are for a second FinFET device and wherein saidfirst FinFET device and said second FinFET device are of a same type. 4.The method of claim 1, further comprising: forming a first gatestructure around said first plurality of fins; and forming a second gatestructure around said second plurality of fins.
 5. The method of claim1, wherein said patterned hard mask layer is comprised of siliconnitride, said liner material is comprised of aluminum oxide and saidlayer of insulating material is comprised of silicon dioxide.
 6. Themethod of claim 1, wherein performing said process operation comprisesperforming a chemical mechanical polishing process operation.
 7. Themethod of claim 1, wherein said first thickness is greater than saidsecond thickness and said first height is greater than said secondheight.
 8. The method of claim 1, wherein said first thickness is lessthan said second thickness and said first height is less than saidsecond height.
 9. The method of claim 1, wherein said liner materialpositioned adjacent said first plurality of fins comprises multiplelayers of liner material, said liner material positioned adjacent saidsecond plurality of fins comprises a single layer of liner material,said first thickness is greater than said second thickness and saidfirst height is greater than said second height.
 10. The method of claim1, wherein said liner material positioned adjacent said first pluralityof fins comprises a single layer of liner material, said liner materialpositioned adjacent said second plurality of fins comprises a singlelayer of liner material, said first thickness is greater than saidsecond thickness and said first height is greater than said secondheight.
 11. The method of claim 1, wherein said liner materials are madeof the same material.
 12. The method of claim 1, wherein said secondetching process results in said liner material adjacent said firstplurality of fins having a first generally U-shaped liner positioned ata bottom of each of said trenches adjacent said first plurality of finsthat exposes at least one of said first plurality of fins to said firstheight.
 13. The method of claim 12, wherein said second etching processresults in said liner material adjacent said second plurality of finshaving a second generally U-shaped liner positioned at a bottom of eachof said trenches adjacent said second plurality of fins that exposes atleast one of said second plurality of fins to said first height.
 14. Amethod of forming an integrated circuit product, comprising: forming apatterned hard mask layer above a semiconductor substrate; performing atleast one first etching process through said patterned hard mask layerto form a plurality of trenches in said semiconductor substrate thatdefine a first fin above a first active region of said substrate and asecond fin above a second active region of said substrate; forming linermaterial adjacent to at least said first fin to a first thickness;forming liner material adjacent to at least said second fin to a secondthickness that is different from said first thickness; forming a layerof insulating material in said trenches adjacent said liner materialsand above said patterned hard mask layer; performing at least oneprocess operation to remove portions of said layer of insulatingmaterial and to expose portions of said liner materials; performing atleast one second etching process to remove portions of said linermaterials and said patterned hard mask layer, wherein removal of saidliner materials results in exposing said first fin to a first height andsaid second fin to a second height that is different from said firstheight; and performing at least one third etching process on said layerof insulating material to thereby define a reduced-thickness layer ofinsulating material.
 15. A method of forming a FinFET device,comprising: forming a patterned hard mask layer above a semiconductorsubstrate; performing at least one first etching process through saidpatterned hard mask layer to form a plurality of trenches in saidsemiconductor substrate that define a first plurality of fins above afirst active region of said substrate and a second plurality of finsabove a second active region of said substrate; forming a first linerlayer in said plurality of trenches, above said hard mask and adjacentto at least said first and second plurality of fins; performing a secondetching process to remove at least portions of said first liner layerpositioned adjacent said second plurality of fins; forming a secondliner layer above said first liner layer and adjacent to said secondplurality of fins; forming a layer of insulating material in saidtrenches above said first and second liner layers and above saidpatterned hard mask layer; performing a process operation to removeportions of said layer of insulating material and to expose portions ofat least said second liner layer; performing at least one third etchingprocess to remove portions of said first and second liner layers andsaid patterned hard mask layer, wherein removal of portions of saidfirst and second liner layers results in exposing at least one of saidfirst plurality of fins to a first height and exposing at least one ofsaid second plurality of fins to a second height that is less than saidfirst height; and performing at least one fourth etching process on saidlayer of insulating material to thereby define a reduced-thickness layerof insulating material.
 16. The method of claim 15, wherein said firstplurality of fins are for a first FinFET device of a first type and saidsecond plurality of fins are for a second FinFET device of a second typethat is opposite to said first type.
 17. The method of claim 15, whereinsaid first plurality of fins are for a first FinFET device and saidsecond plurality of fins are for a second FinFET device and wherein saidfirst FinFET device and said second FinFET device are of a same type.18. The method of claim 15, further comprising: forming a first gatestructure around said first plurality of fins; and forming a second gatestructure around said second plurality of fins.
 19. The method of claim15, wherein said first and second liner layers have the same approximatethickness.
 20. The method of claim 15, wherein said first and secondliner layers are made of the same material.
 21. An integrated circuitproduct, comprising; a first FinFET device formed above a first activeregion of a semiconductor substrate, said first FinFET devicecomprising: a first plurality of fins, at least one of said firstplurality of fins having a first fin height; a first trench positionedbetween said first plurality of fins, said first trench having a firstgenerally U-shaped liner material positioned in a bottom of said firsttrench; and a second FinFET device formed above a second active regionof said semiconductor substrate, said second FinFET device comprising: asecond plurality of fins, at least one of said second plurality of finshaving a second fin height, wherein said first and second fin heightsare different; and a second trench positioned between said secondplurality of fins, said second trench having a second generally U-shapedliner material positioned in a bottom of said second trench.
 22. Thedevice of claim 21, wherein said first generally U-shaped liner materialdefines a first cavity and said second generally U-shaped liner materialdefines a second cavity, wherein the device further comprises a layer ofinsulating material positioned at least partially in said first andsecond cavities.
 23. The device of claim 22, wherein said layer ofinsulating material is positioned entirely within one of said first andsecond cavities.
 24. The device of claim 21, wherein said firstgenerally U-shaped liner material has a first thickness and said secondgenerally U-shaped liner material has a second thickness that isdifferent from said first thickness.
 25. The device of claim 24, whereinsaid first thickness is greater than said second thickness.
 26. Thedevice of claim 24, wherein said first thickness is less than saidsecond thickness.
 27. The device of claim 26, further comprising: afirst gate structure around said first plurality of fins; and a secondgate structure around said second plurality of fins.
 28. The device ofclaim 21, wherein said first fin height is greater than said second finheight.
 29. The device of claim 21, wherein said first fin height isless than said second fin height.
 30. The device of claim 21, whereinsaid liner material positioned adjacent said first plurality of finscomprises multiple layers of liner material, said liner materialpositioned adjacent said second plurality of fins comprises a singlelayer of liner material and said first height is greater than saidsecond height.
 31. The device of claim 26, wherein said liner materialpositioned adjacent said first plurality of fins comprises a singlelayer of liner material, said liner material positioned adjacent saidsecond plurality of fins comprises a single layer of liner material andsaid first height is greater than said second height.
 32. An integratedcircuit product, comprising; a first FinFET device positioned above afirst active region of a semiconductor substrate, said first FinFETdevice comprising a first fin having a first fin height; and a secondFinFET device positioned above a second active region of saidsemiconductor substrate, said second FinFET device comprising a secondfin having a second fin height, wherein said first and second finheights are different.